Let’s try to simulate a non-trivial circuit in Racket using the techniques proposed in the previous post.

Virgule is a 32-bit RISC processor core that supports most of the base instruction set of the RISC-V specification (RV32I). It was initially designed and implemented in VHDL to serve as an illustration for the digital electronics course that I teach. The VHDL source code is not publicly available yet but you can get an overview of what Virgule is by using its web-based simulator emulsiV and reading its documentation.

In the series My first domain-specific language with Racket, I have created a simple hardware description language (HDL) called Tiny-HDL. The intent of the series was to illustrate the techniques for creating a domain-specific language in Racket, from parsing to code generation, with a focus on name resolution and semantic checking. In this post, I will focus on the runtime aspects: how can we simulate a digital circuit description in Racket.