Let’s try to simulate a non-trivial circuit in Racket using the techniques proposed in the previous post.

Vermicel is a 32-bit RISC processor core that supports most of the base instruction set of the RISC-V specification (RV32I). It was initially designed and implemented in VHDL to serve as an illustration for the digital electronics course that I teach. The VHDL source code is not publicly available yet but you can get an overview of what Vermicel is by using its web-based simulator emulsiV and reading its documentation.

In the series My first domain-specific language with Racket, I have created a simple hardware description language (HDL) called Tiny-HDL. The intent of the series was to illustrate the techniques for creating a domain-specific language in Racket, from parsing to code generation, with a focus on name resolution and semantic checking. In this post, I will focus on the runtime aspects: how can we simulate a digital circuit description in Racket.

This is the final step of my Racket DSL implementation roadmap. It consists in promoting Tiny-HDL as a standalone language with two flavors: a Lisp-like syntax and a custom syntax.

Racket offers a sophisticated module system that allows to organize a program into multiple files. In this step, we will show a solution to take advantage of Racket modules in a DSL.

In this post, we add more semantic checks. A circuit description will be considered correct if it respects some common electronic design rules.

The semantic checker for Tiny-HDL will be written in two steps. In the name resolution step, the checker introduces scopes in the abstract syntax tree, and uses them to map each named reference to the corresponding declaration.

In step 1, I have written the full adder example in Racket, following a few mapping rules to express the concepts of the Tiny-HDL language. The next step consists in writing a code generator that implements these mapping rules so that we can generate Racket code automatically.

In the previous post, I have sketched an informal specification of a small hardware description language called Tiny-HDL. Our goal is to execute circuit descriptions, written in Tiny-HDL, on the Racket platform. Which means that we need to implement a compiler from Tiny-HDL to Racket.

As explained in the proposed language implementation roadmap, we will start in the execution step, with a hand-written Racket example program that implements the Tiny-HDL concepts.

For many years, I have felt an attraction to languages from the Lisp family, but I was held back by two concerns: my indecisiveness about which variant to learn, and the lack of a personal project to implement with it. Recently, I have started drafting the Hardware Description Language (HDL) of my dreams and I have decided to try Racket, a Scheme variant that is also advertised as a language-oriented programming language.