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Posts for tag: RISC-V

Simulating digital circuits in Racket

A RISC-V core in Racket

Guillaume Savaton

Let’s try to simulate a non-trivial circuit in Racket using the techniques proposed in the previous post.

Virgule is a 32-bit RISC processor core that supports most of the base instruction set of the RISC-V specification (RV32I). It was initially designed and implemented in VHDL to serve as an illustration for the digital electronics course that I teach. The VHDL source code is not publicly available yet but you can get an overview of what Virgule is by using its web-based simulator emulsiV and reading its documentation.

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